Honored ContributorHi all,
I am migrating a design from Xilinx Spartan 6 to Cyclone 4. I am wondering what is equivalent in Cyclone 4 for the BUFIO and BUFR. I have read the cyclone 4 document and found nothing about regional clock network.Do I have to use one of the Global clock network to drive the FIFO bridging the IO clock domain and the Global clock domain? Thanks a lot! Jeff
Honored ContributorYes. I believe there are 20-30 global clocks depending on the device. I haven't seen any issues where that wasn't enough(although I'm sure possible).
Honored ContributorThanks Rysc,
I am porting a Edge Aligned Single Data Rate Source Synchronouse design from Xilinx to Cyclone 4. In Xilinx, the source clock is fed into a BUFIO pin and inverted to capture the data pins. The source clock pin feeds a BUFR regional clock, which drives a FIFO to bridge to global clock domain. So, in Cyclone 4, I can connect the source clock to any PIN and invert and then drive the data pin registers, and also connect the source clock pin to GCLK and drive cross clock domain FIFO. Am I correct ? Beside, your guide on TimeQuest is really a pleasant to read.Honored ContributorGlad you like the TimeQuest User Guide.
Ideally the clock will come in on a dedicated clock pin. In your RTL just use that clock to latch the input data on the falling edge, and then feed it into the FIFO. You don't have to instantiate a global buffer or anything, as it will automatically get promoted to that since your driving the clock ports of registers.Honored ContributorMany thanks Rysc,
Looks like that my thinking has been very limited by Xilinx terms. The BUFIO of Xilinx has very limited reach， so I have to use BUFR or sth to extend the source clock to reach FIFO. In Cyclone 4, things are very simple and straight forward: Just use the source clock signal to connect everything. I like that!Honored ContributorGood to hear.
