What are the cyclone 4 counterparts for Xilinx BUFIO and BUFR

Thanks Rysc,

I am porting a Edge Aligned Single Data Rate Source Synchronouse design from Xilinx to Cyclone 4.

In Xilinx, the source clock is fed into a BUFIO pin and inverted to capture the data pins. The source clock pin feeds a BUFR regional clock, which drives a FIFO to bridge to global clock domain.

So, in Cyclone 4, I can connect the source clock to any PIN and invert and then drive the data pin registers, and also connect the source clock pin to GCLK and drive cross clock domain FIFO.

Am I correct ?

Beside, your guide on TimeQuest is really a pleasant to read.