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Honored Contributor
Honored ContributorWhat are the cyclone 4 counterparts for Xilinx BUFIO and BUFR
Hi all, I am migrating a design from Xilinx Spartan 6 to Cyclone 4. I am wondering what is equivalent in Cyclone 4 for the BUFIO and BUFR. I have read the cyclone 4 document and foun...
Altera_ForumHonored Contributor
Honored ContributorGlad you like the TimeQuest User Guide.
Ideally the clock will come in on a dedicated clock pin. In your RTL just use that clock to latch the input data on the falling edge, and then feed it into the FIFO. You don't have to instantiate a global buffer or anything, as it will automatically get promoted to that since your driving the clock ports of registers.
