Forum Discussion
Altera_Forum
Honored Contributor
11 years agoMany thanks Rysc,
Looks like that my thinking has been very limited by Xilinx terms. The BUFIO of Xilinx has very limited reach, so I have to use BUFR or sth to extend the source clock to reach FIFO. In Cyclone 4, things are very simple and straight forward: Just use the source clock signal to connect everything. I like that!