What are the advantages and disadvantages of using VHDL versus Verilog to build a FPGA?

Hi,

"I've already asked this question in another thread, but I think it may be buried too far for most people to see it. I'm trying to build a hardware sorting machine on a FPGA. I haven't coded very much of it, but what I've written is in VHDL. What are the pros and cons of coding something like this in VHDL, versus Verilog?" - - - - - - - For comparison between VHDL & verilog HDL, just go through the features of the languages from their reference manual, even simply you can search online for the difference.

"And are there other hardware description languages besides those two in common use? Also, are there on-line forums for language-related questions I might have in designing my hardware in VHDL? And for language-related questions I might have in designing my hardware in Verilog?" - - - - - - - some times System verilog language is also used but it`s majorly used for verification. If you search online for VHDL, verilog even for System verilog & verification methodologies related Forum, you can see number of options are available.

" Does Intel Quartus Prime work just as well for hardware designed in VHDL as for hardware designed in Verilog?"- - - - - - Just search for the VHDL, Verilog & System verilog online training from link below,

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

Regards,

Vicky

Verilog vs. VHDL: the short answer is that you can use either and get the same results. Sometimes, the company you work for dictates which language you must use. Verilog is popular in the USA, but VHDL is used by US military/government and a lot in Europe (don't know why). But really, it's up to you. Verilog, IMO, is easier to learn and use, but it's also easier to get away with bad design practices. VHDL is much stricter in how you use it, but you can be much more precise in how you define things. It is also much harder to get away with bad design practices. Personally, I prefer Verilog because it's easier to write and quicker to create a synthesizable design.

Other languages: there are older languages like Altera's own AHDL, but today, it's really only Verilog or VHDL.

You can post language-related questions here, but just Googling will find you forums that are HDL specific.

Verilog vs. VHDL in Quartus: here's the biggest difference in choosing one or the other. If you are using the Lite or Standard editions of Quartus, they don't support the latest VHDL standard, 2008. The Pro edition has much more extensive VHDL 2008 support. All editions support Verilog and Verilog 2005 (SystemVerilog), but again, the Pro edition has added support and enhanced language checks.

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