What are the advantages and disadvantages of using VHDL versus Verilog to build a FPGA?

Hi,

"I've already asked this question in another thread, but I think it may be buried too far for most people to see it. I'm trying to build a hardware sorting machine on a FPGA. I haven't coded very much of it, but what I've written is in VHDL. What are the pros and cons of coding something like this in VHDL, versus Verilog?" - - - - - - - For comparison between VHDL & verilog HDL, just go through the features of the languages from their reference manual, even simply you can search online for the difference.

"And are there other hardware description languages besides those two in common use? Also, are there on-line forums for language-related questions I might have in designing my hardware in VHDL? And for language-related questions I might have in designing my hardware in Verilog?" - - - - - - - some times System verilog language is also used but it`s majorly used for verification. If you search online for VHDL, verilog even for System verilog & verification methodologies related Forum, you can see number of options are available.

" Does Intel Quartus Prime work just as well for hardware designed in VHDL as for hardware designed in Verilog?"- - - - - - Just search for the VHDL, Verilog & System verilog online training from link below,

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

Regards,

Vicky