Warning: Node: WRN was determined to be a clock but was found without an associated clock assignment.

Then your code is correct and you should false path the WRN input. It's not a good idea to have a truly asynchronous input like this, especially a control signal. You might want to consider synchronizing WRN in the FPGA with a clock through a synchronizer chain of registers.

Is there a PROCESS statement above the code you've posted?

#iwork4intel

WRN is asynchronous, so you can't use set_input_delay with it. You have to false path it.

#iwork4intel

So which paths is the timing analyzer showing as unconstrained clocks?

You need false paths or set_input[output]_delay on all I/O to fully constrain the design.

If you are outputting a clock (why do you say it's asynchronous?), that's basically a source synchronous interface. You need to create a generated clock constraint on the output port.

There is a lot going on here. I highly recommend you check out the timing analyzer online trainings, especially "Required SDC constraints":

https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html?courseType=Online&language=English&keywords=timing%20analyzer

#iwork4intel

You've written this code such that WRN looks like a clock instead of an enable. You should have something like this:

process (clk)

begin

if rising_edge(clk) then

if WRN='1' then

datum <= adbus(15 downto 0);

Then of course you need an SDC constraint for clk. WRN would have a set_input_delay constraint.

As for why you're getting a no fit error, it most likely would not be because of this issue, which is just a warning. Something else is using up resources in your design.

#iwork4intel

Hello sstrell,

Thank you for your reply.

This is an asynchronous interface between Microcontroller and FPGA. The FPGA waits for WRN's rising edge and then reads the data on bus. Since there is no clock involved, I cannot modify the code as per your suggestion.

Is there any other way you think to solve this?

One hint: I will check if I can proceed with reading data when WRN = '0' instead? This wouldnt confuse the compiler about WRN.

I will look into the fitter error, no need to worry about that now.

Sure sstrell, I will add multiple registers as synchronizers for WRN.

YES. There is a PROCESS statement to derive the rising edge signal.

edge: PROCESS (contclk, dff_clearn)

BEGIN

IF dff_clearn = '0' THEN

wrn_d <= '0' ;

ELSIF contclk'EVENT AND contclk= '1' THEN

wrn_d <= wrn;

END IF;

END PROCESS;

Also please comment on the syntax of "set_input_delay" SDC command. Im getting an error as explained in earlier post.

Hello,

Following up on this, should all the asynchronous inputs to the pins of FPGA shall be considered false paths? and hence no input constraints can be applied to them?

I would like to know how to treat the synchronous outputs of FPGA, that are read asynchronously by the microcontroller. Should these FPGA outputs be constrained with output delays?

The unconstrained paths report from timing analyser after compilation shows the below results. Kindly let me know how can I completely constrain my design.

Property Setup Hold

Illegal Clocks 0 0

Unconstrained Clocks 2 2

Unconstrained Input Ports 60 60

Unconstrained Input Port Paths 2570 2570

Unconstrained Output Ports 88 88

Unconstrained Output Port Paths 1305 1305

Thank you again!

Should all the asynchronous inputs to the pins of FPGA shall be considered false paths? Yes. If they are not launched by a clocked device (that clock is a virtual clock that you need to constrain, by the way), they are asynchronous and can't use set_input_delay. And set_input_delay always uses the external clock (the virtual clock) for the -clock argument to define the launch edge for the input analysis.

Should these FPGA outputs be constrained with output delays? If they are latched by the downstream device by a clock (another virtual clock), then again you use set_output_delay. If not, you could just false path them.

Can you indicate what paths are being considered clock and I/O paths that need to be constrained? Can you post your .sdc?

#iwork4intel

Hello sstrell,

Please find the IO interface in my top level module:

Synchronous IO:

i_contclk : IN STD_LOGIC; --32Mhz main clock

i_clk1 : IN STD_LOGIC; -- dedicated clock for speecial application 1, derived from external oscillator

i_clk2 : IN STD_LOGIC; -- dedicated clock for speecial application 2 derived from external oscillator

i_clk3 : IN STD_LOGIC; -- dedicated clock for speecial application 3 derived from external oscillator

i_clk4 : IN STD_LOGIC; -- dedicated clock for speecial application 4 derived from external oscillator

o_int : OUT STD_LOGIC; -- Interrupt signal from FPGA to Microcontroller

o_sts : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); --Enable signals for external multiplexer switch IC

CM : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- feedback from the above multiplexer IC. I dont know if this is synchronous input. Mux doesnt has any clocks connected to it.

o_watchdog : OUT STD_LOGIC; -- Time-out signal of Watchdog to Microcontroller

o_WR_n : OUT STD_LOGIC; --Write Enable to external ASIC

o_RD_n : OUT STD_LOGIC; --Read Enable to external ASIC

o_CEPROM : OUT STD_LOGIC; --EEPROM Enable

o_abt : OUT STD_LOGIC; --Sampling signal to ADC from FPGA

Asynchronous IO:

TOUT : IN STD_LOGIC; -- Data Request Signal from external system. This system is placed far from my FPGA board

EXTCLR : IN STD_LOGIC; -- Reset input from a push button

DISCR_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- Asynchronous discrete inputs

-- BUS signals to communicate with Microcontroller (All Asynchronous)

AD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

ALE : IN STD_LOGIC;

CLEARN : IN STD_LOGIC;

WRN : IN STD_LOGIC;

RDN : IN STD_LOGIC;

--ADC Signal

FLASH :IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from ADC. Is this considered synchronous? FPGA supplies control signals to ADC from clocked processes and we know the time within which the ADC provides data on its pins

--DAC Signal( All synchronous)

o_dac_clk : OUT STD_LOGIC; -- clock supplied to DAC

o_DAC_data : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- Data supplied to DAC

Here are the .sdc file commands:

create_clock -name { i_contclk} -period 31.25 -waveform { 0.000 15.625 } [get_ports { i_contclk}]

create_clock -name {i_clk1} -period 31.25 -waveform { 0.000 15.625 } [get_ports{ i_clk1}]

create_clock -name {i_clk2} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk2}]

create_clock -name {i_clk3} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk3}]

create_clock -name {i_clk4} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk4}]

set_false_path -from [get_pins i_contclk] -to [get_pins WRN]

set_false_path -from [get_pins i_contclk] -to [get_pins ALE]

set_false_path -from [get_pins i_contclk] -to [get_pins RDN]

set_false_path -from [get_pins i_contclk] -to [get_pins CLEARN]

set_false_path -from [get_pins i_contclk] -to [get_pins AD]

Really appreciate for taking time to look into this.

After reading your comments, my next steps are:

Almost all the inputs are asynchronous, so I will false path them. Please let me know if I should consider the external oscillator clocks as synchronous or asynchronous.

I will create virtual clocks based on the devices latching the synchronous data from FPGA. I would like to know how to calculate the delay value in set_output_delay command.