Forum Discussion
Occasional ContributorWarning: Node: WRN was determined to be a clock but was found without an associated clock assignment.
Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
Occasional ContributorHello sstrell,
Please find the IO interface in my top level module:
Synchronous IO:
i_contclk : IN STD_LOGIC; --32Mhz main clock
i_clk1 : IN STD_LOGIC; -- dedicated clock for speecial application 1, derived from external oscillator
i_clk2 : IN STD_LOGIC; -- dedicated clock for speecial application 2 derived from external oscillator
i_clk3 : IN STD_LOGIC; -- dedicated clock for speecial application 3 derived from external oscillator
i_clk4 : IN STD_LOGIC; -- dedicated clock for speecial application 4 derived from external oscillator
o_int : OUT STD_LOGIC; -- Interrupt signal from FPGA to Microcontroller
o_sts : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); --Enable signals for external multiplexer switch IC
CM : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- feedback from the above multiplexer IC. I dont know if this is synchronous input. Mux doesnt has any clocks connected to it.
o_watchdog : OUT STD_LOGIC; -- Time-out signal of Watchdog to Microcontroller
o_WR_n : OUT STD_LOGIC; --Write Enable to external ASIC
o_RD_n : OUT STD_LOGIC; --Read Enable to external ASIC
o_CEPROM : OUT STD_LOGIC; --EEPROM Enable
o_abt : OUT STD_LOGIC; --Sampling signal to ADC from FPGA
Asynchronous IO:
TOUT : IN STD_LOGIC; -- Data Request Signal from external system. This system is placed far from my FPGA board
EXTCLR : IN STD_LOGIC; -- Reset input from a push button
DISCR_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); -- Asynchronous discrete inputs
-- BUS signals to communicate with Microcontroller (All Asynchronous)
AD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
ALE : IN STD_LOGIC;
CLEARN : IN STD_LOGIC;
WRN : IN STD_LOGIC;
RDN : IN STD_LOGIC;
--ADC Signal
FLASH :IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data from ADC. Is this considered synchronous? FPGA supplies control signals to ADC from clocked processes and we know the time within which the ADC provides data on its pins
--DAC Signal( All synchronous)
o_dac_clk : OUT STD_LOGIC; -- clock supplied to DAC
o_DAC_data : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); -- Data supplied to DAC
Here are the .sdc file commands:
create_clock -name { i_contclk} -period 31.25 -waveform { 0.000 15.625 } [get_ports { i_contclk}]
create_clock -name {i_clk1} -period 31.25 -waveform { 0.000 15.625 } [get_ports{ i_clk1}]
create_clock -name {i_clk2} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk2}]
create_clock -name {i_clk3} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk3}]
create_clock -name {i_clk4} -period 31.25 -waveform { 0.000 15.625 } [get_ports {i_clk4}]
set_false_path -from [get_pins i_contclk] -to [get_pins WRN]
set_false_path -from [get_pins i_contclk] -to [get_pins ALE]
set_false_path -from [get_pins i_contclk] -to [get_pins RDN]
set_false_path -from [get_pins i_contclk] -to [get_pins CLEARN]
set_false_path -from [get_pins i_contclk] -to [get_pins AD]
Really appreciate for taking time to look into this.
After reading your comments, my next steps are:
Almost all the inputs are asynchronous, so I will false path them. Please let me know if I should consider the external oscillator clocks as synchronous or asynchronous.
I will create virtual clocks based on the devices latching the synchronous data from FPGA. I would like to know how to calculate the delay value in set_output_delay command.
