Forum Discussion
Occasional ContributorWarning: Node: WRN was determined to be a clock but was found without an associated clock assignment.
Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
Super ContributorSo which paths is the timing analyzer showing as unconstrained clocks?
You need false paths or set_input[output]_delay on all I/O to fully constrain the design.
If you are outputting a clock (why do you say it's asynchronous?), that's basically a source synchronous interface. You need to create a generated clock constraint on the output port.
There is a lot going on here. I highly recommend you check out the timing analyzer online trainings, especially "Required SDC constraints":
#iwork4intel
NShan12Hello sstrell,
ALE and WRN were shown as unconstrained clocks since these were directly connected to clock pin of FF. The rising and falling edges of these were used to latch the data. Now its no more shown as unconstrained, since I used an edge detection signal and then latching the data.
You need false paths or set_input[output]_delay on all I/O to fully constrain the design. - Yes, I will make sure this is done.
You need to create a generated clock constraint on the output port. - Absolutely, this was somewhere down in the mind but I can say, I never understood the real meaning of this. It makes sense now, I will use this command.
Thank you for the link! I will go through all the trainings and work it out. 😄
