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Warning: Node: WRN was determined to be a clock but was found without an associated clock assignment.
- 6 years ago
Update:
I created a rising edge detector signal 'WRN_re'
WRN_re <= (WRN_d XOR WRN) AND WRN; -- WRN_d is the delayed version of WRN (generated from a clocked process)
I used this signal to read data from the bus instead. The warning still exists. After checking the RTL viewer, I clearly see that WRN is never connected to clock pin of any flip flop.
Now I do not understand why the comiler is considering WRN as a clock and throwing the warning.
Also the new error pops up:
Error (332000): Following required options are missing: -clock
---------------------------------------------------------------------------
Usage: set_input_delay [-h | -help] [-long_help] [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
-h | -help: Short help
-long_help: Long help with examples and possible return values
-add_delay: Create additional delay constraint instead of overriding previous constraints
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects
---------------------------------------------------------------------------
while executing
"set_input_delay –clock CONTCLK_IN 5 [get_ports WRN]"
The command in bold is the SDC command I have used for WRN. Is the syntax of the SDC command right? I followed the Quartus tutorial to write this command.
Requesting your help. Thank you in advance!
Should all the asynchronous inputs to the pins of FPGA shall be considered false paths? Yes. If they are not launched by a clocked device (that clock is a virtual clock that you need to constrain, by the way), they are asynchronous and can't use set_input_delay. And set_input_delay always uses the external clock (the virtual clock) for the -clock argument to define the launch edge for the input analysis.
Should these FPGA outputs be constrained with output delays? If they are latched by the downstream device by a clock (another virtual clock), then again you use set_output_delay. If not, you could just false path them.
Can you indicate what paths are being considered clock and I/O paths that need to be constrained? Can you post your .sdc?
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