Warning: Ignored filter: *ws_dgrp|dffpipe_5e9:dffpipe9|dffe10a (RapidIO)

Ignore them. When TimeQuest starts running, you'll see a message that says "Reading HDL embedded constraints"(or something like that), and this is where these .sdc constraints come from. They cut paths between domains within the dual-clock FIFO. I've seen these before and not sure why they don't match up. In general, you've probably already cut timing between the clocks in your .sdc, and so the false path is done already. This is only a concern if you have failing paths between domains inside the DCFIFO, which can be fixed by cutting timing between the asynchronous clock domains, i.e. cutting at the clock level rather than the path level.