Warning : Inferring latches for signal or varialbe

Hi all,

Am new to VHDL and this forum.

When executing my VHDL code am getting following warning "Inferring latches for signal or variable "datain_mem" which holds its previous value in one or more paths"

"Inferring latches for signal or variable "datain_reg" which holds its previous value in one or more paths"

my code is

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity datapath is

port( reset, clk, start: in std_logic;

mainout: out std_logic_vector( 7 downto 0 )

);

end datapath;

architecture struct of datapath is

component controller is

port( clock,GO,rst: in std_logic;

wr,memdrive,aludrive,ld_x,ld_y: out std_logic;

funct_in:in std_logic_vector(7 downto 0);

addr: out std_logic_vector(7 downto 0);

funct: out std_logic_vector(2 downto 0)

);

end component;

component memory is

port ( clock,rst,wr,memdrive : in std_logic;

data_in,address : in std_logic_vector(7 downto 0);

data_out : out std_logic_vector(7 downto 0)

);

end component;

component alu is

port( reset, clk, l_x,l_y,aludrive: in std_logic;

xm,ym: in std_logic_vector( 7 downto 0 );

func_m: in std_logic_vector( 2 downto 0);

aluout: out std_logic_vector( 7 downto 0 )

);

end component;

signal address: std_logic_vector( 7 downto 0 );

signal wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s: std_logic;

signal funct_s: std_logic_vector(2 downto 0);

signal mainbus : std_logic_vector( 7 downto 0 );

signal datain_mem ,datain_reg: std_logic_vector( 7 downto 0 );

signal dataout_m,math_out,dataxout,datayout : std_logic_vector( 7 downto 0 );

begin

Control:controller port map(clk,start,reset,wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s,mainbus,address,funct_s);

Mem: memory port map( clk,reset,wr_s,memdrive_s,datain_mem,address,dataout_m);

Arithlogic: alu port map( reset,clk,ld_x_s,ld_y_s,aludrive_s,datain_reg,datain_mem,funct_s,math_out);

mainout <= math_out;

process(clk,wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y_s,mainbus,dataout_m,math_out)

begin

if (wr_s = '1') then

datain_mem <= mainbus ;

end if;

if (memdrive_s='1' ) then

if (wr_s = '0') then

mainbus <= dataout_m;

else

mainbus<=(others=>'Z');

end if;

if (ld_x_s='1' or ld_y_s='1') then

datain_reg <= mainbus;

end if;

elsif(aludrive_s = '1') then

mainbus <= math_out;

else

mainbus<=(others=>'Z');

end if;

end process;

end struct;

Can anyone pls help me resolve this issue....

Thanks in advance