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Altera_Forum's avatar
Altera_Forum
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15 years ago

Warning : Inferring latches for signal or varialbe

Hi all, Am new to VHDL and this forum. When executing my VHDL code am getting following warning "Inferring latches for signal or variable "datain_mem" which holds its previous value in one ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi all,

Thanks for ur answer. its works.

i got some warning like Tri state node(s) do not directly drive top-level pins

Is this warning matters or not... coz when trying to generate functional simulation netlist, am not getting the wave from file.

Can anyone pls help me to resolve this issue...

Thanks in advance.....:) :) :)