Forum Discussion
Altera_Forum
Honored Contributor
16 years agoWarning : Inferring latches for signal or varialbe
Hi all, Am new to VHDL and this forum. When executing my VHDL code am getting following warning "Inferring latches for signal or variable "datain_mem" which holds its previous value in one ...
Altera_Forum
Honored Contributor
16 years agoHi all,
Thanks for ur answer. its works. i got some warning like Tri state node(s) do not directly drive top-level pins Is this warning matters or not... coz when trying to generate functional simulation netlist, am not getting the wave from file. Can anyone pls help me to resolve this issue... Thanks in advance.....:) :) :)