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Altera_Forum's avatar
Altera_Forum
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15 years ago

Warning : Inferring latches for signal or varialbe

Hi all, Am new to VHDL and this forum. When executing my VHDL code am getting following warning "Inferring latches for signal or variable "datain_mem" which holds its previous value in one ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Change the asynchronous process to a synchronous one.

process(clk,wr_s,memdrive_s,aludrive_s,ld_x_s,ld_y _s,mainbus,dataout_m,math_out)

begin

if rising_edge(clk) then

if (wr_s = '1') then

datain_mem <= mainbus ;

.....

....

...

--- Quote End ---

and you can remove all signals except clk from the sensitivity list.