Want help in adding delay in Verilog,using Altera de2 FPGA

Uzairsaeed702

I think that what is being asked for here is how to add delay in actual hardware in the FPGA.

While one could certainly look at the IO Elements and send signals into and out of the FPGA and get a certain small amount of incremental delay - I do not think that is what is really being looked for.

If I understand what you are looking for correctly - here is what you will need to do in order to get a "certain amount ofdelay" on a signal that will "move" through the FPGA.

You will need a clocked signal that will get registered into a Flip Flop in the FPGA - the "delay" will be based on the clock rate - let's say that the clock rate is once every 100 ns, then if you want to delay the signal 500 ns, you would simply stack up the signal through 5 Flip Flops (registers) in order to delay the incoming signal by 500 ns.

This a very crude way to do it and I will leave it to others to teach you a better method for latching a signal and then 'counting' a certain number of clocks before allowing the signal to propagate to the next register (Flip flop) or output.

Is this what you are asking how to do?

After you reply - I am certain others will be able to advance your desing effort further.

Avatar