Altera_ForumHonored Contributor15 years agoWant help in adding delay in Verilog,using Altera de2 FPGA Asslam o ALukum Hey can any one help me, i added an delay but its not running on FPGA... please anyone help me out how to add delay that is executble on FPGA board ThanksShow More
Recent DiscussionsRequest for COO infoJTAG Chain Broken on Agilex 7-I Dev KitFeasibility to implement 350MHz LVDS + soft-CDR on Cyclone 10LPQuestionWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?