Video Clock Output to SDI II in Agilex 5

Wincent,

in that document you linked, it references a parameter setting "Enable active video data protocols" which is not an option when I try to create the core. 

Also, from Section 5.4.3 Intel FPGA Video Streaming Interface:

This IP can optionally transport video using the Altera FPGA streaming video protocol,
which uses the industry standard AXI4-Stream protocol with extensions for
transporting metapacket and active video data.

It allows interfacing to Altera FPGA Video and Vision Processing (VVP) Suite IPs or
other AXI4-Stream compliant third-party video IPs.

Note: This feature is only available for Agilex 7 F-Tile device.
 

So how do we do this with the Agilex 5?

thanks - rob