Forum Discussion
Hi,
Which device that you are targeting ?
From the title , I assume is Agilex 5 right..
IF Agilex 5 , it is using GTS SDI II, instead of older version of SDI II.
For the signal name please refer to https://www.intel.com/content/www/us/en/docs/programmable/823539/25-3/gts-quick-reference.html
Check the similar signal and try to connect accordingly. IF there is no error shown in Quartus then it shall be something valid.
Regards,
Wincent
Wincent,
in that document you linked, it references a parameter setting "Enable active video data protocols" which is not an option when I try to create the core.
Also, from Section 5.4.3 Intel FPGA Video Streaming Interface:
This IP can optionally transport video using the Altera FPGA streaming video protocol,
which uses the industry standard AXI4-Stream protocol with extensions for
transporting metapacket and active video data.
It allows interfacing to Altera FPGA Video and Vision Processing (VVP) Suite IPs or
other AXI4-Stream compliant third-party video IPs.
Note: This feature is only available for Agilex 7 F-Tile device.
So how do we do this with the Agilex 5?
thanks - rob
- Wincent_Altera2 months ago
Regular Contributor
Hi Rob,
I try to check back , unfortunately none for Agilex 5 at the moment.
Regards,
Wincent - Wincent_Altera2 months ago
Regular Contributor
Hi Rob,
Is there anything else you think I can better assist you ?
Regards,Wincent
- aucamera11 month ago
New Contributor
sorry, been out on holiday leave
I would like some assistant on how Altera intends one to hook the Clock Video Output of the VVVP to the SDI II.