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aucamera1's avatar
aucamera1
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6 months ago

Video Clock Output to SDI II in Agilex 5

I'm trying to output a video chain using the VVP cores but I can't figure out how to connect the VCO to the SDI II. on Quartus 18.1, the VCO core would output vid_data[19..0], vid_trs, and vid_ln[10...
Core Logic
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
6 months ago

Hi,

Which device that you are targeting ?
From the title , I assume is Agilex 5 right.. 
IF Agilex 5 , it is using GTS SDI II, instead of older version of SDI II.
For the signal name please refer to https://www.intel.com/content/www/us/en/docs/programmable/823539/25-3/gts-quick-reference.html

Check the similar signal and try to connect accordingly. IF there is no error shown in Quartus then it shall be something valid.

Regards,
Wincent

aucamera1's avatar
aucamera1
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6 months ago

Wincent,

in that document you linked, it references a parameter setting "Enable active video data protocols" which is not an option when I try to create the core. 

Also, from Section 5.4.3 Intel FPGA Video Streaming Interface:

This IP can optionally transport video using the Altera FPGA streaming video protocol,
which uses the industry standard AXI4-Stream protocol with extensions for
transporting metapacket and active video data.


It allows interfacing to Altera FPGA Video and Vision Processing (VVP) Suite IPs or
other AXI4-Stream compliant third-party video IPs.


Note: This feature is only available for Agilex 7 F-Tile device.
 

So how do we do this with the Agilex 5?

thanks - rob