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aucamera1's avatar
aucamera1
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2 months ago

Video Clock Output to SDI II in Agilex 5

I'm trying to output a video chain using the VVP cores but I can't figure out how to connect the VCO to the SDI II. on Quartus 18.1, the VCO core would output vid_data[19..0], vid_trs, and vid_ln[10...
Core Logic
Wincent_Altera's avatar
Wincent_Altera
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2 months ago

Hi,

Which device that you are targeting ?
From the title , I assume is Agilex 5 right.. 
IF Agilex 5 , it is using GTS SDI II, instead of older version of SDI II.
For the signal name please refer to https://www.intel.com/content/www/us/en/docs/programmable/823539/25-3/gts-quick-reference.html

Check the similar signal and try to connect accordingly. IF there is no error shown in Quartus then it shall be something valid.

Regards,
Wincent

  • aucamera1's avatar
    aucamera1
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    2 months ago

    yes, the Agilex 5

    yes, i'm using hte GTS SDI II

    there are no similar pins.  Especially if trying to connect the two cores in Platform Designer.

    is there no example of how to use the GTS SDI II with the VVP cores?  The two connected seems like it would be the most common use case.

    thanks

    -rob

    • Wincent_Altera's avatar
      Wincent_Altera
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      2 months ago

      Hi Rob,

      At the moment, we do not offer direct example to connect it.
      My best suggestion is compare both signal name between SDI II IP vs GTS SDI II IP and try it.
      The signal function will be pretty much similar , just need to be extra careful to check the signal requirement.

      Regards,
      Wincent

      • aucamera1's avatar
        aucamera1
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        1 month ago

        Hi Wincent,

        unfortunately, as I stated earlier, there are no similar pins between the two IP cores.

  • aucamera1's avatar
    aucamera1
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    2 months ago

    Wincent,

    in that document you linked, it references a parameter setting "Enable active video data protocols" which is not an option when I try to create the core. 

    Also, from Section 5.4.3 Intel FPGA Video Streaming Interface:

    This IP can optionally transport video using the Altera FPGA streaming video protocol,
    which uses the industry standard AXI4-Stream protocol with extensions for
    transporting metapacket and active video data.


    It allows interfacing to Altera FPGA Video and Vision Processing (VVP) Suite IPs or
    other AXI4-Stream compliant third-party video IPs.


    Note: This feature is only available for Agilex 7 F-Tile device.
     

    So how do we do this with the Agilex 5?

    thanks - rob

    • Wincent_Altera's avatar
      Wincent_Altera
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      2 months ago

      Hi Rob,

      I try to check back , unfortunately none for Agilex 5 at the moment.

      Regards,
      Wincent

    • Wincent_Altera's avatar
      Wincent_Altera
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      2 months ago

      Hi Rob,

      Is there anything else you think I can better assist you ?

      Regards,

      Wincent

      • aucamera1's avatar
        aucamera1
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        1 month ago

        sorry, been out on holiday leave

        I would like some assistant on how Altera intends one to hook the Clock Video Output of the VVVP to the SDI II.