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Altera_Forum's avatar
Altera_Forum
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15 years ago

vht test bench examples

Hello,

I am specifying altera to generate a .vht test bench for my vhdl project. I want to modify this test bench so that I can specify the input signals to be some value at different times instead of the current undefined (U).

SIGNAL clk : STD_LOGIC;

.

.

clk : IN STD_LOGIC;

.

.

.

clk => clk,

.

-- code that executes only once

WAIT;

END PROCESS init;

always : PROCESS

-- optional sensitivity list

-- ( )

-- variable declarations

BEGIN

clk <='1'; wait for 10 ns;

clk <='0'; wait for 10 ns;

-- code executes for every event on sensitivity list

--WAIT;

I have been trying to find for hours some example modified test bench files that I can work off. The above code does not change the clock signal in the signal viewer in modelsim-altera at all.

thank you

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Sorry, the wait signal in my code is commented out. I copied your code exactly as you specified in the section the vht generated test bench says to put code you want to run indefinetly. However it is still not showing up on my signal viewer.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    The above code does not change the clock signal in the signal viewer in modelsim-altera at all.

    --- Quote End ---

    Because you have told the process to wait (stop) after toggling the signal once. For a clock, what you want is 

    
process
begin
   clk <= '0';
   wait for 10 ns;
   clk <= '1';
   wait for 10 ns;
end process;
    and the process will repeat in an infinite loop repeating these waits, and hence generate a clock.

    Cheers,

    Dave