Altera_Forum
Honored Contributor
Honored Contributorvhdl
i have a vhdl code and a verilog code for a game.can i use both in the same project and how can i couple them? thx.
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes you can. There is a chapter in the user manual about "mixed language synthesis". --- Quote End --- If you want to use the Altera Modelsim edititons for simualtion keep in mind that only single language ( Verilog OR VHDL) is supported.. Kind regards GPK
