Vhdl

hello, I have to must carry through a program VHDL for me to allow to write in the file (tableau). But I have a problem because I not mean the new file (tableau) after simulation. Tank you a all to hepl me.

LIBRARY ieee ;

use std.textio.all;

USE ieee.std_logic_1164.all ;

LIBRARY std;

ENTITY table5 IS

PORT ( init: IN STD_LOGIC;

acquit: OUT STD_LOGIC );

END table5 ;

ARCHITECTURE testTableau OF table5 IS

BEGIN

PROCESS (init)

file tableau : text open write_mode is "d:\russell\tableau.txt";

variable pixel_1 : line;

variable pixel_2 : line;

BEGIN

write(pixel_1, string'("writing from tableau.txt"));

writeline(tableau, pixel_1);

write(pixel_2, string'("writing from tableau.txt"));

writeline(tableau, pixel_2);

acquit <= not init;

END PROCESS;

END testTableau;