From what I read the circuit will measure the number of clock pulses.
Each clock pulse has a fixed duration (T = 1/fclk).
First try to understand what your circuit is. This means input and output signals and internal circuitry.
You need:
1) A signal that enables counting (input)
2) A clock (input)
3) A reset (input)
4) The duration of the measured pulse (output: how many bit?)
The circuit could be a simple counter wich counts the high duration of a signal.
The Altera example for a counter (Verilog) is:
module counter
(
clk,
reset,
result,
ena
);
input clk;
input reset;
input ena;
output result;
reg result;
always @(posedge clk or posedge reset)
begin
if (reset)
result = 0;
else if (ena)
result = result + 1;
end
endmodule
I think this is a good start.