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Honored Contributor
Honored Contributor[VHDL] Synthesis of 'if' loop(s)
Hello, I have a specific problem.
Does a number of instructions under if loop affect synthesis and fitter results? For example, I have a several simple instructions, such as adding or several shifters - independent from each other - and I put them all under one process(clk). Could fitter results be different, if I divide it and put all groups of dependent registers under separate processes? For example, change process:process(clk)
begin
if rising_edge(clk) then
a0 <= a1;
a1 <= a2;
b0 <= b1;
b1 <= b2;
end if;
end process;process(clk)
begin
if rising_edge(clk) then
a0 <= a1;
a1 <= a2;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
b0 <= b1;
b1 <= b2;
end if;
end process;
