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Honored Contributor
Honored Contributor[VHDL] Synthesis of 'if' loop(s)
Hello, I have a specific problem. Does a number of instructions under if loop affect synthesis and fitter results? For example, I have a several simple instructions, such as adding or several shif...
Altera_ForumHonored Contributor
Honored ContributorOk, thanks very much, I wasn't sure about this. I just need to know any things, that may affect design.
