[VHDL] Synthesis of 'if' loop(s)

The two bits of code you posted would provide identical results, but personally I would just use the first process and separate the two shifters with some good comments, saying they are different shifters.

The synthesisor/fitter does a very good job at combining related logic, whether its in the same if block or not, or whether its in completly separate processes. The synthesisor basically does and massive boolean equation reduction. If statements boil down to simple logic gates.

Great examples of where synthesis and fitter results can differ - if you have several memories all addressed using the same address bus, the RTL viewer will show several separate altsyncrams, but when fitted it may use only a single M9K. It is very good at packing.