VHDL std_logic_vector Comparisons

FvM did best understand and respond to my original post.

But Tricky brought up a good point. My std_logic_vector does represent an integer. An integer that represents a calculated distance from a sensor. I set this integer to zero when the distance is not in a valid range for my application. That way I only need 1 "done" signal to accompany the "distance" integer to know when the distance is ready to be read. I don't need an additional "valid" signal to indicate that the distance is in my valid range, since it will be zero if it's not.

I haven't coded in VHDL for a couple of years. Can integers be synthesizable entity ports? I have my "distance" as a std_logic_vector instead of an integer cuz I need to pass it b/t entities.