VHDL std_logic_vector Comparisons

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I'm going to use AND_REDUCE()

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Yes, that's better.

P.S.: I understood "What's the best way" is asking for a convenient way without writing too much text. VHDL is verbose enough anyway. For this simple reason, the original poster did not want to define compare strings and similar stuff. The compiler will convert any equivalent expression to anding all bits.

P.P.S.: I completely agree with Tricky, that numeric quantities should use numeric types and also numeric constants.