VHDL state to entity

Like I said I always verify before I post. My code:

State : out std_logic_vector( 1 downto 0) ;
StateN : out natural ;
...
State <= std_logic_vector( to_unsigned( states_camerastatusLED'pos( smp ) , 2 ) ) ;
StateN <= states_camerastatusLED'pos( smp )  ;

What error did you get? Did you include the IEEE numeric_std library?

The natural data type will synthesize to a 31bit-wide vector. You can see this in the 'Tools->RTL Viewer' window. You can constrain the range of the natural to 7 in your case, and you will end up with just 3 pins synthesized.

CurrentStateOut : out natural range 0 to 7 ;

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Is natural data type synthesizable

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Yes, josyb implied this by mentioning the default size of 31 bits. Something like natural range 0 to 7 would be more appropriate for synthesis.

But you should consider, that a type with implicite bit definition has some disadvantages in pin assignment.

Hi,

Please see my code below (coded as per the current thread) and the error log;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
entity statemachine is
  port (
         clk        : in std_logic;
         rst        : in std_logic;
         proceed    : in std_logic;
         data_out   : out std_logic;
         outn_state : out natural range 0 to 7;
         outp_state : out std_logic_vector(2 downto 0)
       );
end entity;
architecture SYNTH of statemachine is
type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7);
attribute syn_enum_encoding: string;
attribute syn_enum_encoding of state : type is "000 001 010 011 100 101 110 111";
signal cur_state, nxt_state : state;
begin
outn_state <= std_logic_vector(to_unsigned(state'pos(cur_state),3));
outp_state <= state'pos(cur_state);

The error log is copied below;

************************************************************************

vhdlan state_machine.vhd

Synopsys 1076 VHDL Analyzer

Version D-2010.06-SP1-8 -- Aug 13, 2011

Copyright (c) 1991-2010 by Synopsys Inc.

ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.

and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.

Parsing design file 'state_machine.vhd'

Error-[SEQSTMTASSIGNTYPE] Type mismatch

state_machine.vhd, 31

SYNTH

outn_state <= std_logic_vector(to_unsigned(state'pos(cur_state),3));

^

The assignment statement target data type does not match the source data

type. The target data type is 'Anonymous subtype of INTEGER' and is

declared by 'PACKAGE STD.STANDARD'. The source data type is

'STD_LOGIC_VECTOR' and is declared by 'PACKAGE IEEE.STD_LOGIC_1164'.

Error-[SEQSTMTASSIGNTYPE] Type mismatch

state_machine.vhd, 32

SYNTH

outp_state <= state'pos(cur_state);

^

The assignment statement target data type does not match the source data

type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and

is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is

'UNIVERSAL INTEGER' and is declared by 'PACKAGE STD.STANDARD'.

"state_machine.vhd": errors: 2; warnings: 0.

************************************************************************

Please guide me to clear the error.

Regards,

freak

also remove:

use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

they are deprecated and (may) conflict with the numeric_std library

Thanks a lot Josyb. Its workig.

Regards,

freak

You mean, by default the tool uses one-hot encoding.

Regards,

freak

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You mean, by default the tool uses one-hot encoding.

Regards,

Jaseel

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If you have more than 3 states, the default is one hot.