VHDL state to entity

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You mean, by default the tool uses one-hot encoding.

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You can watch the implemented encoding in the state maschine viewer. One state hot is said to be most effective for FPGA implementations. It uses more state variable registers but less LE's for the state machine logic and achieves highest speed.

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You can watch the implemented encoding in the state maschine viewer. One state hot is said to be most effective for FPGA implementations. It uses more state variable registers but less LE's for the state machine logic and achieves highest speed.

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I think it may be more prudent to say can achieve the highest speed. E.g. if you compare a few 32 bit numbers in your state machine speed will drop considerably and then the encoding doesn't really matter that much any more. I try to pre-register the inputs to a state machine, it keeps the transition equations simple (sometimes even readable), easy to simulate (I tend to separate state machines into a separate file) and achieves highest speed. E.g. in a downcounter I set a registered IsZero flag when count is one and we see a count enable. Instead of 32 bits we then have a single IsZero input to the state machine