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Altera_Forum
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15 years ago

VHDL state to entity

Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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You mean, by default the tool uses one-hot encoding.

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You can watch the implemented encoding in the state maschine viewer. One state hot is said to be most effective for FPGA implementations. It uses more state variable registers but less LE's for the state machine logic and achieves highest speed.