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Altera_Forum
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15 years ago

VHDL state to entity

Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Is natural data type synthesizable

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Yes, josyb implied this by mentioning the default size of 31 bits. Something like natural range 0 to 7 would be more appropriate for synthesis.

But you should consider, that a type with implicite bit definition has some disadvantages in pin assignment.