Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me know how to do this. Regards, freak

add an output port with your favorite name, then curr_state_out <= curr_state; This should keep your customer happy.

Hi kaz, This is throwing error. I had already tried this. The error is copied below, Error-[SEQSTMTASSIGNTYPE] Type mismatch ../dut/state_machine.vhd, 33 SYNTH outp_state <= cur_state; ^ The assignment statement target data type does not match the source data type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is 'STATE' and is declared by 'ARCHITECTURE SYNTH'. "../dut/state_machine.vhd": errors: 1; warnings: 0. This occurs because our state variable is user defined and ouptut port is std_logic_vector. The state definition is copied below; type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7); signal cur_state, nxt_state : state; Any idea to override this or any convesion function. Regards, freak

Hi, Good point. There might be some of those special tool statements to do that(Only FvM knows those secrets) but if it is me I will regenerate a bit of logic: case cur_state is when idle => out_p <= "000"; when s1 => out_p <= "001"; ...etc. i.e. you convert it to numerical value onto std_logic_vector. Regards

CurrentStateOut : out std_logic_vector( ceil(log2( number of states )) - 1 downto 0) ; --- CurrentStateOut <= std_logic_vector( to_unsigned( state'pos(curr_state) , ceil(log2( number of states )) ) ; You have to replace the ceil(log2( number of states )) in the port declaration by a fixed number as the size of 'state' is only defined until later in the architecture section. If the output is only required for simulation or documentation purposes you could define the output port as a natural: CurrentStateOut : out natural ; ... CurrentStateOut <= state'pos( curr_state) ; simple, and you don't have to modify the code in case the 'state' definition changes during the design. The only drawback is that the natural is represented as a 31-bit vector, so you may want to restrict the range of the natural.

Thanks JosyB, In layman terms like myself I believe you mean: port declaration: CurrentStateOut : out std_logic_vector(2 downto 0); then in assignment section: CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state),3)); Hopefully that will do if tool support doesn't get in the way.

VHDL state to entity | Altera Community

22 Replies

Altera_Forum
Honored Contributor
15 years ago
Hi kaz,

This is throwing error. I had already tried this.

The error is copied below,

Error-[SEQSTMTASSIGNTYPE] Type mismatch
../dut/state_machine.vhd, 33
SYNTH

outp_state <= cur_state;
^
The assignment statement target data type does not match the source data
type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and
is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is
'STATE' and is declared by 'ARCHITECTURE SYNTH'.

"../dut/state_machine.vhd": errors: 1; warnings: 0.

This occurs because our state variable is user defined and ouptut port is std_logic_vector.
The state definition is copied below;

type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7); signal cur_state, nxt_state : state;

Any idea to override this or any convesion function.

Regards,
freak
Altera_Forum
Honored Contributor
15 years ago
add an output port with your favorite name, then

curr_state_out <= curr_state;

This should keep your customer happy.

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VHDL state to entity

22 Replies

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