VHDL state to entity

Hi kaz,

This is throwing error. I had already tried this.

The error is copied below,

Error-[SEQSTMTASSIGNTYPE] Type mismatch

../dut/state_machine.vhd, 33

SYNTH

outp_state <= cur_state;

^

The assignment statement target data type does not match the source data

type. The target data type is 'Anonymous subtype of STD_LOGIC_VECTOR' and

is declared by 'PACKAGE IEEE.STD_LOGIC_1164'. The source data type is

'STATE' and is declared by 'ARCHITECTURE SYNTH'.

"../dut/state_machine.vhd": errors: 1; warnings: 0.

This occurs because our state variable is user defined and ouptut port is std_logic_vector.

The state definition is copied below;

type state is (IDLE, ST1, ST2, ST3, ST4,ST5, ST6, ST7);
signal cur_state, nxt_state : state;

Any idea to override this or any convesion function.

Regards,

freak