Hello everybody I'm new in VHDL and I'm doing a project with DE2 board In the project I need to build a robot. My first step was to design a ASM and from that to take out the FSM which i did (hopefully I did it good enough) The second step is to check one of my ASM and I choose my engine control ASM I wrote a program in VHDL using quartus and burn it into my board Instead of using the motors from the beginnig the idea was to used the board's led using a PWM generator that will create a "running led" effect for a curtain direction and in change it in a push of a button but it didn't work. Can anybody tell me what I did wrong? I think it's in the pin assignment

The code: library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity Pwm is Port ( Rst : In std_logic; Clk : In std_logic; s : In std_logic; Enable : in std_logic; Led : buffer std_logic_vector (7 downto 0); Pwm : Out std_logic ); attribute altera_chip_pin_lc : string; attribute altera_chip_pin_lc of clk : signal is "@N2"; attribute altera_chip_pin_lc of rst : signal is "@G26"; attribute altera_chip_pin_lc of Led : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21"; attribute altera_chip_pin_lc of s : signal is "@N25"; attribute altera_chip_pin_lc of Enable : signal is "@N26"; end entity Pwm; Architecture arc_Pwm of Pwm is signal Counter : std_logic_vector (16 downto 0); signal DC : std_logic_vector (16 downto 0); begin PwmReg: process (Clk,Rst,s) begin if (Rst='1') then Counter <= (others=>'0'); Pwm <= '0'; Led <= (others=>'0'); DC <= conv_std_logic_vector(32678,17); --duty cycle 50% elsif rising_edge(Clk) then if (Enable='1') then if (Counter = 50000) then Counter <= (others => '0'); elsif (Counter < DC) then Counter <= Counter + 1; Pwm <= '1'; if (s = '1') then led <= Led + 1; if(Led = "11111111") then Led <= (others=>'0'); end if; else led <= Led - 1; if(Led = "00000000") then Led <= (others=>'1'); end if; end if; else Counter <= Counter + 1; Pwm <= '0'; end if; else Pwm <= '0'; end if; end if; end process PwmReg; end architecture arc_Pwm;

Hi rotemkim, I am changing the name of your thread title to something more specific to your topic of discussion. Also I'm moving it to the General Altera Discussion category. The "Altera Forum Website Related" category is for questions about the forum website or its use, not the use of devices or tools from Altera. For help with your problem, it would be easier for others to give you advice if you point out some debug steps you've taken. Have you simulated the VHDL code to see if it behaves as you expect? The pinout check is also a good start, but checking the code in simulation is better start. You may want to add a sanity check output pin that drives an LED on the board. Divide your input clock to a slow speed <= a few Hz and assign it to the output pin that drives the LED. Start small and work your way back to full design functionality.

your right I do need to simulate the code first... I wrote a tb for the code but i dont see any waveform way? library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use std.textio.all; --use ieee.std_logic_textio.all; ------------------------------------------------------------------------------ entity tb_pwm is end entity tb_pwm; ------------------------------------------------------------------------------ architecture arc_tb_pwm of tb_pwm is signal Clk : std_logic := '0'; -- signal Rst : std_logic := '0'; -- signal Sw : std_logic_vector (2 downto 0):= "000"; -- signal Enable : std_logic := '0'; -- signal Pwm : std_logic; -- signal Led : std_logic_vector(7 downto 0); -- begin test : entity work.pwm port map ( Clk => Clk, Rst => Rst, Enable => Enable, Sw => Sw, Pwm => Pwm, Led => Led ); Clk <= not Clk after 10 ns; Rst <= '1' after 20 ns; process begin wait until Rst = '1'; wait until rising_edge(Clk); Enable <= '1'; wait until rising_edge(clk); Sw(0) <= '1'; Sw(1) <= '0'; Sw(2) <= '0'; wait for 100ms; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '1'; Sw(2) <= '0'; wait for 100ms; wait until rising_edge(clk); Sw(0) <= '0'; Sw(1) <= '0'; Sw(2) <= '1'; wait for 100ms; wait until rising_edge(clk); Enable <= '0'; wait for 100ms; wait until rising_edge(clk); Rst <='0'; wait for 100ms; end process; end architecture arc_tb_pwm;

The testbench doesnt match the PWM code you posted. In your PWM code, there is no SW bus. One other things: When you use a std_logic_vector as a counter (I highly recommend you dont, use the numeric_std library instead of std_logic_arith/unsigned) you dont need to reset it if it gets to max. It will roll over if you get to all ones and roll under if you get to all zeros. You only have to check the value if LED was an integer rather than std_logic_vector.

Your right I changed the code a little. library IEEE; use IEEE.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; Entity Pwm is Port ( Rst : In std_logic; Clk : In std_logic; Sw : In std_logic_vector (2 downto 0); Enable : in std_logic; Led : out std_logic_vector (7 downto 0); Pwm : Out std_logic); attribute altera_chip_pin_lc: string; attribute altera_chip_pin_lc of Clk : signal is "@N2"; attribute altera_chip_pin_lc of Rst : signal is "@G26"; attribute altera_chip_pin_lc of Led : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21, @AC21"; attribute altera_chip_pin_lc of Sw : signal is "@N25,@N26, @P25"; attribute altera_chip_pin_lc of Enable: signal is "@AE14"; end entity Pwm; Architecture arc_Pwm of Pwm is signal Counter : std_logic_vector (16 downto 0); signal DC : std_logic_vector (16 downto 0); signal Rd_led : std_logic_vector (7 downto 0); begin PwmReg: process (Clk,Rst,Sw) begin if (Rst='1') then Counter <= (others=>'0'); Pwm <='0'; Led <= (others=>'0'); Rd_led <= (others=>'0'); DC <= conv_std_logic_vector(32678,17); --duty cycle 50% elsif rising_edge(Clk) then if (Enable='1') then if (Counter = 50000) then Counter <= (others => '0'); if (Sw(0) = '1') and (Sw(1) = '0') and (Sw(2) = '0') then Rd_led <= Rd_led + 1; elsif (Sw(0) = '0') and (Sw(1) = '1') and (Sw(2) = '0') then Rd_led <= Rd_led - 1; end if; Led <= Rd_led; elsif (Counter < DC) then Counter <= Counter + 1; Pwm <= '1'; else Counter <= Counter + 1; Pwm <= '0'; end if; else Pwm <= '0'; end if; end if; end process PwmReg; end architecture arc_Pwm; I am don't know what numeric std library does can you clarify please, and why is it better to use rather then std_logic in general and specific in this code

VHDL robot design not working | Altera Community

34 Replies

Altera_Forum
Honored Contributor
15 years ago
I can't really help you if I don't know what went wrong with your code
I can tell you the steps that I had made in order to create a working code
1. Understand your goals
2. Pick your components according to your goals
3. Understand how the components works
4. Create asm
5. Design a logic circuit
6. Write it in vhdl
Hope it was helpful
Altera_Forum
Honored Contributor
15 years ago
--- Quote Start ---
Hello everybody I'm new in VHDL and I'm doing a project with DE2 board

In the project I need to build a robot.

My first step was to design a ASM and from that to take out the FSM which i did (hopefully I did it good enough)
The second step is to check one of my ASM and I choose my engine control ASM
I wrote a program in VHDL using quartus and burn it into my board
Instead of using the motors from the beginnig the idea was to used the board's led using a PWM generator that will create a "running led" effect for a curtain direction and in change it in a push of a button
but it didn't work.
Can anybody tell me what I did wrong?

I think it's in the pin assignment
--- Quote End ---

Hi there
I am very new in VHDL I want to write a code for line following robot , but I faced a lot of problems because I started from zero. I spent already more than two months to learn it.
when I started to write the code I got stuck and I couldn't know how to start.

I tried to check from the internet but I didn't find any thing, then I found your code for robot using VHDL. could you please help me with that if you have done it successfully
Altera_Forum
Honored Contributor
15 years ago
I attaching me designs just in case they are a bit different by now but they could deliver the general idea
Altera_Forum
Honored Contributor
15 years ago
thanks you helped me a lot
Altera_Forum
Honored Contributor
15 years ago
I compiled your code and looked at the rtl veiwer (tools -> netlist viewers -> rtl netlist. This shows you the logic derrived from your code). When I saw all the logic had dissapeared (except for latched versions of the input for the leds) I knew something was up because theres nothing wrong fundamentally with the code. I then worked out that 1s/20ns is 50mil, and realised counter, at 17 bits, was not enough to cover 50mil. Because Quartus knows this too, it removed all the logic dependant on it because it never does anything.

changing the counter length wont do much other than increase the number of registers used. It will work fine.
Altera_Forum
Honored Contributor
15 years ago
first thanks.

second how did you come to that from the warrnings

third is it good design to change the counter?
Altera_Forum
Honored Contributor
15 years ago
its because the counter signal is only 17 bits, and so not big enough to count to 50million. The synthesisor knows it can never reach 50million, and removes all the logic. You would need 26 bits for that.
Altera_Forum
Honored Contributor
15 years ago
i just changed the generic time from 100 ms to give the led longer delay
Entity Pwm is
generic (
DC : time:=1 sec;
clock_period: time:=20 ns
);
Altera_Forum
Honored Contributor
15 years ago
that sounds like you've modified the code and removed the clock, or done something that means you're not creating a proper register.
Altera_Forum
Honored Contributor
15 years ago
1. Warning (10631): VHDL Process Statement warning at Pwm.vhd(37): inferring latch(es) for signal or variable "Led", which holds its previous value in one or more paths through the process

2. Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "Led[0]" is stuck at GND - for al of the code pins

3. Warning: Design contains 6 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "Rst"

4. Warning: Found 9 output pins without output pin load capacitance assignment
Info: Pin "Led[0]" has no specified output pin load capacitance -- assuming
default load capacitance of 0 pF for timing analysis

5. Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.

6. Warning: No paths found for timing analysis

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VHDL robot design not working

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