VHDL robot design not working

1. Warning (10631): VHDL Process Statement warning at Pwm.vhd(37): inferring latch(es) for signal or variable "Led", which holds its previous value in one or more paths through the process

2. Warning: Output pins are stuck at VCC or GND

Warning (13410): Pin "Led[0]" is stuck at GND - for al of the code pins

3. Warning: Design contains 6 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "Rst"

4. Warning: Found 9 output pins without output pin load capacitance assignment

Info: Pin "Led[0]" has no specified output pin load capacitance -- assuming

default load capacitance of 0 pF for timing analysis

5. Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.

6. Warning: No paths found for timing analysis