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Altera_Forum
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15 years ago

VHDL robot design not working

Hello everybody I'm new in VHDL and I'm doing a project with DE2 board In the project I need to build a robot. My first step was to design a ASM and from that to take out the FSM which i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

its because the counter signal is only 17 bits, and so not big enough to count to 50million. The synthesisor knows it can never reach 50million, and removes all the logic. You would need 26 bits for that.