VHDL robot design not working

I compiled your code and looked at the rtl veiwer (tools -> netlist viewers -> rtl netlist. This shows you the logic derrived from your code). When I saw all the logic had dissapeared (except for latched versions of the input for the leds) I knew something was up because theres nothing wrong fundamentally with the code. I then worked out that 1s/20ns is 50mil, and realised counter, at 17 bits, was not enough to cover 50mil. Because Quartus knows this too, it removed all the logic dependant on it because it never does anything.