VHDL robot design not working

The testbench doesnt match the PWM code you posted. In your PWM code, there is no SW bus.

One other things:

When you use a std_logic_vector as a counter (I highly recommend you dont, use the numeric_std library instead of std_logic_arith/unsigned) you dont need to reset it if it gets to max. It will roll over if you get to all ones and roll under if you get to all zeros. You only have to check the value if LED was an integer rather than std_logic_vector.

your right I do need to simulate the code first...

I wrote a tb for the code but i dont see any waveform way?

 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--use std.textio.all;
--use ieee.std_logic_textio.all;
------------------------------------------------------------------------------
entity tb_pwm is
end entity tb_pwm;
------------------------------------------------------------------------------
architecture arc_tb_pwm of tb_pwm is
  signal Clk : std_logic             := '0';  -- 
  signal Rst : std_logic               := '0';  -- 
  signal Sw  : std_logic_vector  (2 downto 0):= "000";    -- 
  signal Enable : std_logic      := '0';  -- 
  signal Pwm : std_logic;                     -- 
  signal Led : std_logic_vector(7 downto 0);  -- 
begin
  
  test : entity work.pwm
    
    port map (
      Clk  => Clk,  
      Rst  => Rst,  
      Enable => Enable, 
      Sw  => Sw,  
      Pwm  => Pwm,  
      Led  => Led );                              
  Clk <= not Clk after 10 ns;
  Rst <= '1'     after 20 ns;
  process
    
  begin
    wait until Rst = '1';
    wait until rising_edge(Clk);
    Enable <= '1';
      wait until rising_edge(clk);
   Sw(0) <= '1';
   Sw(1) <= '0';
   Sw(2) <= '0';
   wait for 100ms;
   wait until rising_edge(clk); 
   Sw(0) <= '0';
   Sw(1) <= '1';
   Sw(2) <= '0';
   wait for 100ms;
      wait until rising_edge(clk);
   Sw(0) <= '0';
   Sw(1) <= '0';
   Sw(2) <= '1';
   wait for 100ms;
      wait until rising_edge(clk);
      Enable <= '0';
   wait for 100ms;
      wait until rising_edge(clk);
      Rst <='0'; 
   wait for 100ms;
  end process;
end architecture arc_tb_pwm;

Hi rotemkim,

I am changing the name of your thread title to something more specific to your topic of discussion. Also I'm moving it to the General Altera Discussion category. The "Altera Forum Website Related" category is for questions about the forum website or its use, not the use of devices or tools from Altera.

For help with your problem, it would be easier for others to give you advice if you point out some debug steps you've taken. Have you simulated the VHDL code to see if it behaves as you expect? The pinout check is also a good start, but checking the code in simulation is better start.

You may want to add a sanity check output pin that drives an LED on the board. Divide your input clock to a slow speed <= a few Hz and assign it to the output pin that drives the LED. Start small and work your way back to full design functionality.

The code:

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

Entity Pwm is

Port ( Rst : In std_logic;

Clk : In std_logic;

s : In std_logic;

Enable : in std_logic;

Led : buffer std_logic_vector (7 downto 0);

Pwm : Out std_logic );

attribute altera_chip_pin_lc : string;

attribute altera_chip_pin_lc of clk : signal is "@N2";

attribute altera_chip_pin_lc of rst : signal is "@G26";

attribute altera_chip_pin_lc of Led : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21";

attribute altera_chip_pin_lc of s : signal is "@N25";

attribute altera_chip_pin_lc of Enable : signal is "@N26";

end entity Pwm;

Architecture arc_Pwm of Pwm is

signal Counter : std_logic_vector (16 downto 0);

signal DC : std_logic_vector (16 downto 0);

begin

PwmReg: process (Clk,Rst,s)

begin

if (Rst='1') then

Counter <= (others=>'0');

Pwm <= '0';

Led <= (others=>'0');

DC <= conv_std_logic_vector(32678,17); --duty cycle 50%

elsif rising_edge(Clk) then

if (Enable='1') then

if (Counter = 50000) then

Counter <= (others => '0');

elsif (Counter < DC) then

Counter <= Counter + 1;

Pwm <= '1';

if (s = '1') then

led <= Led + 1;

if(Led = "11111111") then

Led <= (others=>'0');

end if;

else

led <= Led - 1;

if(Led = "00000000") then

Led <= (others=>'1');

end if;

end if;

else

Counter <= Counter + 1;

Pwm <= '0';

end if;

else

Pwm <= '0';

end if;

end if;

end process PwmReg;

end architecture arc_Pwm;