VHDL robot design not working

The code:

library IEEE;

use IEEE.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

Entity Pwm is

Port ( Rst : In std_logic;

Clk : In std_logic;

s : In std_logic;

Enable : in std_logic;

Led : buffer std_logic_vector (7 downto 0);

Pwm : Out std_logic );

attribute altera_chip_pin_lc : string;

attribute altera_chip_pin_lc of clk : signal is "@N2";

attribute altera_chip_pin_lc of rst : signal is "@G26";

attribute altera_chip_pin_lc of Led : signal is "@AE23, @AF23, @AB21, @AC22, @AD22, @AD23, @AD21";

attribute altera_chip_pin_lc of s : signal is "@N25";

attribute altera_chip_pin_lc of Enable : signal is "@N26";

end entity Pwm;

Architecture arc_Pwm of Pwm is

signal Counter : std_logic_vector (16 downto 0);

signal DC : std_logic_vector (16 downto 0);

begin

PwmReg: process (Clk,Rst,s)

begin

if (Rst='1') then

Counter <= (others=>'0');

Pwm <= '0';

Led <= (others=>'0');

DC <= conv_std_logic_vector(32678,17); --duty cycle 50%

elsif rising_edge(Clk) then

if (Enable='1') then

if (Counter = 50000) then

Counter <= (others => '0');

elsif (Counter < DC) then

Counter <= Counter + 1;

Pwm <= '1';

if (s = '1') then

led <= Led + 1;

if(Led = "11111111") then

Led <= (others=>'0');

end if;

else

led <= Led - 1;

if(Led = "00000000") then

Led <= (others=>'1');

end if;

end if;

else

Counter <= Counter + 1;

Pwm <= '0';

end if;

else

Pwm <= '0';

end if;

end if;

end process PwmReg;

end architecture arc_Pwm;