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Altera_Forum
Honored Contributor
Honored Contributorvhdl querry
Hello Friends, I am new to VHDL and I have a couple of querries. Kindly help me out if possible - 1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into har...
Altera_ForumHonored Contributor
Honored ContributorDear Friend ,
Thank you very much indeed for all the responses. I am just rephrasing my understanding of the clocked sequential circuit used in an earlier post. write_req <= '1'; write_req:process(phy_clk) begin if rising_edge(phy_clk) then if reset_phy_clk = '1' then write_req_1 <= '0'; write_req_2 <= '0'; else write_req_1 <= write_req; write_req_2 <= write_req_1; end if; end if; end process p_data_req; In the above case. at time t0 - it will check rising edge of clock,reset_phy_clk and if both are satisfied t1 - in next cycle write_req_1 <= '0' write_req_2 <= '0'. and it goes into the else part. t2 - write_req_1 <= write_req and write_req_2 <= write_req_1 is done here. Kindly comment if my understanding is correct. So basically it is a synchronous sequential circuit. Reagards, Vinod Karuvat.
