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You mentioned if/else/elsif gets converted to logic. What exactly do u mean by that sir? Is it converted to registers and gates?
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yes
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What I understand is this - inside a process if there is merely an if-else loop it is a combinational design. But, when the if-else is inside a clock (i.e - if rising_edge(clock)..etc) then it is converted into a sequential circuit.
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Yes
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Also why do you say that VHDL code is never executed ?
How does one decide when to use combainational or sequential circuits ? Pls advice me sir.
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VHDL is not executed like software. Software is converted to machine code that is executed in order. VHDL is converted to logic that all runs in parrallel.
All logic circuits are usually combinations of cominatorial and sequential logic. FPGAs can do either.
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Why is it said that using lateches in VHDL is a bad practise ?
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because you cant guarantee the timing. So all sorts of bad things can happen.
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