vhdl querry

Dear Friends,

Thank you for ur response. I am grateful.

--- Quote Start ---

VHDL code is synthesised into gates and registers. So if/elsif/else trees get converted to logic, and if it's inside a clocked process then this logic is registered. All signal assignments take place on every clock cycle. So in this case, write_req_2 is asserted 2 clock cycle after write_req_1. VHDL code is never executed.

--- Quote End ---

You mentioned if/else/elsif gets converted to logic. What exactly do u mean by that sir? Is it converted to registers and gates?

What I understand is this - inside a process if there is merely an if-else loop it is a combinational design. But, when the if-else is inside a clock (i.e - if rising_edge(clock)..etc) then it is converted into a sequential circuit.

Also why do you say that VHDL code is never executed ?

How does one decide when to use combainational or sequential circuits ? Pls advice me sir.

--- Quote Start ---

A latch is a memory device. registers are latches. Latches are created when data is stored and all events on a signal are not covered.

--- Quote End ---

Why is it said that using lateches in VHDL is a bad practise ?

Thank you very much indeed.

Regards,

Vinod Karuvat.