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Hello Friends,
I am new to VHDL and I have a couple of querries. Kindly help me out if possible -
1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into hardware (gates/mux..etc) using a synthesizer. How is an if-else loop created in hardware? The -f-else is a sequential statement. Will it run/be executed at the same clock cycle or the next ? For eg - in the code shown
After how many cycles is write_req_2 asserted ? Can anyone kindly explain this pls? Also, can if-else statements be used to generate/synthesize combinational circuits or only sequential ? Can anyone point me to a doc which shall explain in details how vhdl code is executed(order of execution/timing) and also how it is mapped into hardware ?
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VHDL code is synthesised into gates and registers. So if/elsif/else trees get converted to logic, and if it's inside a clocked process then this logic is registered. All signal assignments take place on every clock cycle. So in this case, write_req_2 is asserted 2 clock cycle after write_req_1. VHDL code is never executed.
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2) What is a latch ?
fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp;
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A latch is a memory device. registers are latches. Latches are created when data is stored and all events on a signal are not covered.
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