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Honored Contributorvhdl querry
Hello Friends, I am new to VHDL and I have a couple of querries. Kindly help me out if possible - 1) If-else loop in VHDL. Now, what I understand is that VHDL code is synthesised into har...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I compile this VHDL but got errors and don't know what wrong with this --- Quote End --- It's a simple syntax error in the port definition. Read the first error message thoroughly and try to understand it. --- Quote Start --- 2) What is a latch ? fifo_o_addr_temp <= fifo_o_addr when fifo_o_addr_temp /= fifo_o_addr else fifo_o_addr_temp; Will doing the above action create a latch ? How so? Is creating a latch in code a good practise or bad? --- Quote End --- It will create nothing except a "wire" assignment fifo_o_addr_temp <= fifo_o_addr, because the code is useless. With a more meaningful condition, it will create a latch. Latches should be avoided in FPGA synthesis, but can't in special cases.
