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Altera_Forum
Honored Contributor
Honored Contributor[VHDL] Problem with signal type "std_logic_vector(0 downto 0)"
Hello, I use IP module, where data bus width is set to '1'. In VHDL code it is declared as type "std_logic_vector(0 downto 0)", but for compiler this is not the same as "std_logic", type of sig...
Altera_ForumHonored Contributor
Honored ContributorYou can keep it as std_logic_vector and access your variable using parenthesis : data(0), no ?
