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Altera_Forum
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15 years ago

VHDL integers initialization and FPGAs

I've started coding in VHDL just less than a year ago - unexperienced student warning! My question is about integer initalization. I own an Altera DE1 board and I've also got some experience wi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Yes, it's the most likely explanation. In case, state would show an illegal bit combination, it can be easily detected in simulation or with signal tap.

The probability of dropping into an illegal state with asynchronous inputs also depends on arbitrary design timing details, it may change with design modifications without a clear relation.

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I see, so what is the best way to prevent this from happening? Synchronize the async. inputs feeded into the FSM ?