Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL integer causing RTL and Gate level simulation difference
I have a general question regarding the use of integers in VHDL. If I have a lot of Array defined, we have to use integer as its index when accessing the arrays. However, when the index is conv...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- integers get value '0' at power on in RTL simulation, while it gets unknown value in real chip. --- Quote End --- Uninitialized integers get assigned the value -2^(N-1), where N is the number of bits in the integer. (At least under VHDL). --- Quote Start --- This is why I want to get rid of all INTEGERs so that I can have a consistently simulation between RTL and GATE. I can capture all my bugs in RTL simulation only. --- Quote End --- I could have sworn one of the first things you're supposed to learn when writing HDL, is to never use integers. That is why there are signed and unsigned types ... of course, that kind of advice does not help when you inherit code ... Cheers, Dave
