VHDL integer causing RTL and Gate level simulation difference

Thanks very much for the reply.

My problem is exactly 'B' gets an unknown value in the design. In RTL simulation, the good 'C' values corresponding to address 0 gets used; while in Gate level simulation, the unknown 'C' gets used.

When there is tons of such logic in your design and we don't do reset our flops as a general principle, it is very hard to catch which one causes the problem in gate level simulation if it is not duplicate-able in RTL simulation.

In general, we don't want to give an initial value to a variable since it is ignored by the synthesize tools.

What we want is to have an exact RTL simulation to avoid debugging problem using gate level simulation.