Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

VHDL: inout port error: multiple drivers

Hello,

I have defined an entity with some ports. One of these ports is defined as follows: 

data    : inout std_logic_vector (63 downto 0);

As you see, I want to read from or write to this port. When I want to write, I simply put some data into the array: 

data<="10101......101010";

If I want to read, I have to reset a port called Dec_nRD: 

Dec_nRD <= '0';

If I disable either the read or write function, my VHDL code works. But if I want to use read and write, then there is a compiler error: 

Error: The node "altera_auto_signaltap_0_DDRAM_Data_signaltap_lcell" has multiple drivers due to the constant driver
Error: The node "altera_auto_signaltap_0_DDRAM_Data_signaltap_lcell" has multiple drivers due to the constant driver
...

As you see, the compiler notices that resetting the Dec_nRD port enables another entity to write to the data bus. Obviously only one entity can write to the data bus at the same time.

What could be the solution?

quartus: Quartus II Version 8.0 Build 215 05/29/2009 SJ Full Version.

os: Windows Vista Enterprise.

device: EP3C25F324C6

family: Cyclone III

Kind regards,

Stefan__

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    The basic fact, that a signal can only have one driver at a time also applies for signals that are connected through the hierarchies. The simple and obvious solution is to have a signal along with the data port, that controls which side is allowed to write to the inout port. It's essential, that the entity not writing to the port must write "ZZZZ" instead. It works like a dual- or multi-drop bidirectional data bus with tristate drivers. Quartus is translating this construct to multiplexers, so another solution is to use unidirectional signals and explicite multiplexers.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    a way round this, and a method that would more accuratly describe real hardware at an internal level (not at the pin-level) would be to have separate in and out ports. inout ports should only really be used at pin levels, and then they should be avoided if possible. You never need internal inout ports.

    The problem should be showing up in simulation. If you drive 2 std_logics together and one of them isnt set to 'Z', you get 'X'. Any time you see 'X' appear in simulation you should investigate and fix the problem, as it usually means the exact problem you have.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    It's essential, that the entity not writing to the port must write "ZZZZ" instead.

    --- Quote End ---

    Yes. I changed my code and then it worked. Thank you.

    --- Quote Start ---

    inout ports should only really be used at pin levels, and then they should be avoided if possible.

    --- Quote End ---

    In this case, inout ports were necessary because my entitiy had to be connected to another entity, which had also an inout port and I couldn't change this because I couldn't see the source code (viewing support not included).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    You never need internal inout ports.

    --- Quote End ---

    They are convenient in some cases though. They are available VHDL constructs and well supported by Quartus. For me, they are a means to wire global data and parameters through the design hierarchies with minimal code typing effort. But there can be only one driver for each data entity, of course